Digital Design

RTL design of digital blocks and subsystems.

Architecture, micro-architecture and SystemVerilog RTL, ready for integration and synthesis.

  • Architecture
  • SystemVerilog RTL
  • IP integration
  • Synthesis
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Typical cases

  • A block or subsystem must go from specification to synthesisable RTL.
  • An existing design needs restructuring or IP integration.
  • The team needs additional RTL design capacity.

Scope

  • Architecture and micro-architecture definition
  • RTL coding in SystemVerilog and Verilog
  • IP and subsystem integration
  • Design reviews and synthesis readiness

Workflow

Design flow
  1. Specification
  2. Micro-architecture
  3. RTL
  4. Integration

Deliverables: Defined per project; for example, a micro-architecture document, RTL source, integration notes and a verification hand-off.