Verification

Functional and formal verification of digital designs.

Verification plans, UVM environments, SVA assertions and formal verification, with coverage metrics for sign-off.

  • UVM
  • SVA
  • Formal verification
  • Coverage and regression
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Typical cases

  • The design needs a verification environment from scratch.
  • Coverage is not converging or the regression is not trusted.
  • Critical blocks need assertions or formal proofs.

Scope

  • Risk-based verification planning
  • UVM testbenches
  • SVA assertions and formal property verification
  • Functional coverage and regression

Workflow

Functional verification
  1. Stimulus
  2. DUT
  3. Monitors
  4. Scoreboard and coverage
Formal verification
  1. Properties
  2. Formal engine
  3. Proof or counterexample

Deliverables: Defined per project; for example, a verification plan, test environment, assertions and coverage reports.